Compound error correction system



Feb. 19, 1963 A. c. Rose:

coMRouNn ERROR coRREcTI-ON SYSTEM 4 Sheets- Sheet 1 Filed Jan. 22, 1959 Feb. 19, 1963 A. c. ROSE 3,078,443

COMPOUND ERROR CORRECTION SYSTEM Filed Jan. 22, 1959 4 Sheets-Sheet 2 61 62 63 64 a; 6 FIG. 2

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Feb. 19, 1963 A. c..Ros1-:

coMPouNn ERRoR CORRECTION SYSTEM 4 sheets-'sheet s Filed Jan. 22. 1959 Feb. 19, 1963 A. c. ROSE 3,078,443

coMPoUND ERROR CORRECTION SYSTEM ALAN C. ROSE United Statesv Patent O 3,078,443 CGMPOUNDERRACRRECTEN SYSTEM Alan C. Rose, Summit, NJ.

(50301Caivin Ave., Ternana, Qali.)

Filed lan. 22,1959, Ser. No. '783,453 17 Claims. (Ci. S40-146.1)

This invention relates to error detection and correction systems for digital data handling systems.

The simplest form of digital error detection involves the-transmission of each digit twice. If the twosignals are different at the detecting point, it is evident that an errorhas occurred. The simplest form of error correction system involves the transmission of each digital signal three times. Errors may Vthen be-corrected on a` two-out-ot-three basis.

InV the tield of digital data transmission, more sophisticated arrangements for detecting or correcting errors are also wellknown. These systems vary in the amount ofA redundancy which is required. Thus, for example, a simple parity checkcircuit for error detection merely involves th'e addition of an eXtra binary digit or bit to groups 'of 'digits to indicate whether the number of ls included in the group is odd or even. More speciiically, the four digit code group 1011 would have a fifth parity bit added to produce the code group llllv/hich includes an even number of "1s. The parity of'each complete group of digits including the check bit is reviewed at the data receiving point, and errorsare indicated by a changey in parity.'

For error correction purposes several parity checks may be made over different sets of 'digits included in the mes sage to be transmitted. Each information digitis included `in vtwo checkv groups. The position of an lerroneous digit may then be located by the erroneous parity check groups. Such a system including four information digits and three check digits is disclosed in R. W. Hamming and E. W. Holbrook Reissue PatentrNo. 23,- 601, granted December 23, 1952,.

Errors may also be corrected by systems in which digits are arrangedV in 'a matrix and parity checks are formed for the rows and columns. Attertransmissionthe digits may be regrouped in matrix, row and column parity check failures. One system of this gene'raltype is disclosed in E. P. G. Wright,'Patent No..2',653,996,` grantedS'epternber 29, 1953.

It has also 'been discovered in thelast yeartor two that errors in many systemtend to be grouped. MoreY particularly, if there is, for exampleyaprobability oil in 100,000 that a given'bit will be changed in transmission, the probability that the next bit will also be wrong may drop to .1 in 10. Thev adverse eilectsofgroups of errors may be reduced (l) by providingfor multipleV error correction through'increasing redundancy or (2) by interleaving the digits of several code groups sothat adjacent erroneous digits will`be part of different codev groups. The individual code groups may be the type dis. closed in the R. W. Hamming et al. patent cited above; This interleaved or interlaced Hamming code andseveral other coding systems are describedin some detailinan article entitled Evaluation of Some ErrorCorrection Methods Applicable to Digital Data Transmission by A. B. Brown and S. T. Meyerspp. 37 through 55 ofjPart 4 of the 1958 IRE National Convention Record. This article also considers error detection plus rerun systems in which code groups are repeated upon the detection of an individual error. In passing, it is noted' that no determination of error rates is made in this last mentioned type of system.

From the foregoing discussion, it is clear that there arey many error detection and error correction schemesavailable to theengineer. A review Vof the various codes, however, reveals the following dilemma. First, the codes and errors identied by the.

ice

which have moderately good errorcorrectingpotentials usually have high-rednn'da r1cies.A In this regard, proposals to add a number of checkbitse'quad-'to the number of` information bits are not uncommon. This reduces the channel capacity by one-half, however, and this is normally not acceptable.

Accordingly, the principal object yof the present `inven-` tion is to detect and correct errors in digital signals without wasting channel space byy unnecessary redundancy.

In accordance with one aspect of the present invention this object is accomplished by sensing the errorV detectionV or correctionrates' of the system and 'switching between schemes which have diierent error detection or correction capabilities. Thus for specific, example a high grade data channel couldnormally` be providedlwi'th` a simple parity checking error detection scheme in which every* sixteenth bitv would-be a check bit. At the detectora` counter would detect the number of parity check failures occurring -within-a given time period. Whenever the error rate exceeds a predetermined toleration level, the channel would be switched over to agloW redundancy error'correction system. In-suehasystem one bit in four or so could be a check bit, and errors may be correctedy satisfactorily as long as they do not occur too close together. If conditions become progressively worse, possibly, as a'result of -sunspot activity or an electricalstorm, `for example, the channel could be'switched over to an interlaced error correcting system or another more powerful form of error correcting arrangement.V These progressive shifts wouldA normally require additional channel space, but the redundancy'would only be that which isactually required to keep the errors Within bounds.

Inswitching frornone error correction scheme to ari-.

other it isuseful to determine the rate `at which errors occurrence of;

are being corrected-andr also therate-'of uncorrectable errors or error patterns. Normally, the signals used in correcting errors are readily available, and thesevsignals mayY be routed to a iirst error counter. This first counter may have its output periodically sensed'and then be reset to give an error rate indication.Y The more sophisticated error correction systems also include ar` rangements for indicating the occurrence o f error patterns whichare beyond the correction capabilities ofthe system. In accordancewith one aspect ofthepresent4 invention the rate of correctable errors andthe ratev ofl occurrencejof` uncorrectableerrors or error bursts are determined and this'information is utilized to increase or decrease the redundancy and theerror'correction capabilities of the digitalv information channel:l

ln accordance with one feature of, the invention a :digital data handlingA system is providedwith compoundjencod-Q ing and'decodingcircuitry inoludingmeans forproviding error detection and correction `schemes of--difierent redun A dancies or of diierent error handling capacities, and switchingcircuitry is provided for` switchingsaid compound encoding and' decoding circuits from one errori do-l tection'and correction scheme 'to another.

In accordance with another-featured the invention the systernas set forth in the preceding paragraph'is provided with one or more circuits rfor'determining the rate of occurrence of errors, andthe switching circuitsare@c on-Y trolled to holdthe errors in the'decodeddatapwithin tolerableA limits. The rate circuits may be, implemented by individual counters which count the correctableand uncorrectable errors, andwhich are periodically'sensedand reset.

Other objects andfeatures, andvarious advantage'sof the invention will become apparent from a consideration of the following detailedi'description and from the drawings, in which:

FTGURE l is a block diagram of a digital transmission system in accordance with the present invention;

auvents FIGURE 2 illustrates one buer storage circuit which may be employed with the system of FIGURE l;

FIGURE 3 shows a circuit diagram of a switching control circuit which may be used in the system of FIV'- URE l;

FIGURE 4 is a logic circuit diagram of the error counters and associated circuits of FIGURE l;

FIGURE 5 shows a simple parity check encoding circuits; and

FIGURE 6 shows a known error correcting circuit, and associated circuits for tying in with the system of FIG- URE 1.

With reference to the drawings, the overall block diagram of one representative system in accordance with present invention includes a digital signal information source 12, and a digital utilization circuit ld. Between the source and utilization circuit are included a buffer storage circuit 16, a compound encoding circuit lf3, a compound decoding circuit 2li, and several special control circuits. These special control circuits include the master source of timing signals 22, the two error counters 24 and 2d for determining error rates, and the error evaluation and switching control circuit 28. Although the counters 2d and 26 and the evaluation and control circuit 28 are shown as separate blocks in FIGURE l, some of the evaluation circuits are closely tied in with the counter output circuits, as developed below.

The illustrative circuit of FIGURE l is shown provided with three or more encoders Sti', 32 and 3ft, and decoders 36, 38 and tu corresponding respectively to the three encoders. While only three sets of encoders and decoders are sho-wn in FIGURE l, it is to be understood that a greater number of encoding and decoding schemes may be employed.

In switching from one encoder scheme to another, a number of switches are required. These switches all through 45' serve to couple the information source, the data link, and the digital utilization circuit to the appropriate encoding and decoding circuits. In addition, the switch d5 supplies signals which correlate the buffer storage timing with the internal timing of the various encoders 30, 32 or 34. The switches il through 4S are operated in synchronism by the switching control circuit 28. Under any given set of operating conditions the switching control circuit 23 will set the switches 4l through 45 to select an encoding and decoding scheme to provide adequate error control. When error conditions change, the changes in error rates are detected by circuits 24 and 26. After a correlation of the change in error rate by circuit 2S, the switches 41 through 45 may be shifted to increase or decrease the error correction capacity of the system. Thus, for example, with an intermediate error rate, the coding scheme represented by the encoder 32 and the decoder 3S may be connected to the information source 12, the data link, and to the digital utilization circuit 14. If the rate of errors decreases, however, it may be possible to use the simpler error checking circuit including the encoder 3) and the decoder 36. As noted in block 31?, the simplest scheme may merely include a parity check and may not provide any error correction whatsoever. As error rates build up, however, a shift would be made under the control of circuit 2S to the encoding scheme represented by encoder 32 and decoder 3S. A further increase in the error rate could result in shifting to a more powerful error correcting scheme as represented by encoder 34 and decoder Such an encoder could involve digital blocks of significant length and a redundancy of 50% or more, by way of example.

FIGURE 2 is a detailed block circuit diagram of a builer storage unit which may be employed in accordance with the present invention. The buffer storage circuit shown in FIGURE 2 is only one of a number of such circuits which could be employed in the implementation of the circuit of FIGURE l. The circuit of FIGURE 2 includes a tape reader 5t), a series of ANI) gates Sil through 56, a shift register 5?, a series of five OR gates 6l through 65, a negation circuit d6 and a delay circuit d. A tape 68 is shown being fed through the tape reader 5ft?. For the purposes of the present example, it is assumed that live binary digits of information are provided at the output of the tape reader 5% each time the reader is advanced. Such signals are provided by standard punched paper tape having a possibility of tive transverse holes. The output leads 7l through i6 from the ta c reader Sil' provide information signals on leads 72 through 76 which represent the binary signals read from the tape. Lead 7l, however, is always energized when signals are read out of tape reader 5u to provide a "i in the initial stage 7E of the shift register The purpose of the marker bit in the first stage of shift register 5S will now be explained. Initially, it may be noted that advance signals are applied on lead titl to each stage of the shift register' 58. These signals must, of couse, be supplied from the encoder, as the rate of advance of the signals varies in accordance with the redundancy of the particular encoding scheme which is employed. Now, as the shift register is emptied by the transmission of information through the switch 41 to the encoder designated 82 in FIGURE 2, the l which was initially in register stage 78 is advanced to the right. It ultimately appears in shift register stage Sd. At this time the remaining stages of the shift register are empty, or have Os stored in them.

he logic circuit including the OR circuits 6l through d5 and the negation circuit 66 is designed to sense the presence of live {s in the first live stages of the shift register 5S, and to provide a signal on lead S6 which this situation occurs. A negation circuit produces an output pulse when no input pulse is applied to it, and produces no output signal when an input pulse or l is supplied to it. Now, with the l initially located in shift register stage 7S, one of the tive OR circuits 611 through 65 is energized as the code group is read out of register 5g, and produces a pulse at the input to the negation circuit 66. Accordingly, no output signal can appear on lead S5. When the l reaches stage S4 of the shift register 58, however, the input signals to all of the OR circuits 6l through 65 are Os, and the negation circuit d6 therefore produces an output signal on lead This serves to advance the tape reader Sii and to supply a new set of binary digits to the leads 72 through '76. Following a brief delay provided by the delay circuit ti, gating signals are applied to the AND circuits 51 through 55. The new group of five binary digits and the marker l are then entered into the shift register 58. It is to be understood that the advance of the tape reader Sd and the feeding of the new data into the shift register 5S occurs during a fraction of a shift interval so that there is no delay in the transmission of digital information to the encoder S2. lt may also be noted that the marker 1 initially stored in shift register stage '7S is cleared from shift register stage 841' by the transmission of new information from the tape reader Sil through the AND circuit Sd to the shift register stage tid. Accordingly, the marker bit is not transmitted on to the encoder 82.

The circuit of FIGURE 3 represents a portion of the error evaluation and switching control circuit 28 of FIG- URE 1. In addition, it shows schematically the tie-in between the circuit and the switches 4l through 45 of FIGURE l. Thus, in FIGURE 3 the switches 4l and 4t2 each include a series of AND gates. More particularly, the switching circuit dll includes the AND gates 91 through 94 and the switching circuit 4.2 includes the AND gates through 93 and the OR circuit 99. The signals from the buffer storage circuit of FIGURE l are applied on lead MP2 to all of the AND gates 91 through 94 in parallel. The enabling input to one of the AND circuits 91 through 9d is supplied by the stepping counter 104. One and only one of the AND circuits 91 through 94|.-isv enabled by signalsfrom the output of. onev of the stages of the stepping counter 104.

The state ofthe stepping counter 194 isl determined. by signals applied to the advance. lead 106 and to the step back. leadliiat the input to thesteppingcounter 1114. Thus, for example, itis initiallyassumed that the stepping counteris in-statel. Under= these conditions,` the-AND circuits 91 and 95A are enabled, thus. selecting-encoder number 1. Now, assuming that error conditions get somewhat worse, an advance pulse isappliedto stepping counter 104 onv lead 106. Uponthe occurrence of this advance pulse, the counter1t4 shifts from its first state to its'second state. Underthese circumstances, the AND circuits 92 andf are enabled, selectingencoder numlber 2. Encoder. number 2 hasmore error correction capabilities than the first encoder and, therefore cancope withthe worsened error conditions.` The applicationA of additional advance signals on lead 166 will step the counter 104. progressively toestates 3, 4 or 5. Eachv advance step Aapplied' to lead Midindicates that the error rateV was. not tolerable under the error conditions and using-the encoding and decoding circuit which was con nectedatthe time thepulsewas receivedon the advance leadfl. In the exampleshown'in. FIGURE 3, four encoders. of progressively increasing error correction capacity.. are provided. Now, when theerror correction capacity.. of. the fourth encoder is exceeded, the stepping counter reaches state 5. Under these conditions, the fourth or nth encoder is maintained energized through .the OR'-circuit.11t. In addition, however, the alarm circuit 112 .is. energized to indicate that the error rate is abovethe toleration level for the entire system.

Thev delay circuits 114, 116, 118 and 120- are provided to indicate the padding delayy necessary inthe course of switching from one error correction scheme to another. Thus, the encodercircuitry associated with each scheme will have anumber of digit periods yof delay .from input tooutput. A delay such as that indicated by the delay units.114, 116-118 or 120 is required in-order to avoid eliminating information digits in-the course of. shifting from one encoding scheme to the next. For easein accommodating such switching, it would be desirable that each of the encoders include the same number of digit periods of delay. This may be accomplished by adding al ser-ies delay circuit within each of the encoders to make. the total delayprovided by eachencoder identical.

FIGURE 4 shows the two error counters 122 and 124. Correctable erreors are received at the OR circuit 125 and applied to the advance lead 126 at the input to the error counter 122. Signals indicating errors which are beyond the capacity of the error correcting scheme which is currently being employed are applied'to the OR circuit 128, and from. this ORcircuit to the advance lead 1300i the counter 124. Theerror evaluation circuits associated with the counters 122 and 124 include the AND circuit 132, the inhibit circuit 134, the OR circuit 136', and the ANDcircuit 138; Input signals to the error evaluation circuitry are supplied from switching networks 141i and 142 at the output of the error counter 122, and from switching network. 144 at the output of error counter 12.4. In addition, signals from the G state of error counter 124A are supplied as one ofthe controlling inputs to the AND circuit 132. A second input lead 146'to the AND circuit 132is enabled by the switching circuit 14S. It is apparent, therefore, that the AND circuit132 is controlled by signals from the state of the counter 124and from the first few stages of counter 122. Thus, if there are nouncorrectable errors, and only a very few correctable errors in a given time interval, the AND circuit 132 is enabled at the time of occurrence of a sense pulse .on lead 150. Following the occurrence of a sense pulse on lead 150, if both of the other two input leads to the AND circuit 132 have been energized, a pulse will be supplied on lead S to step the switching control counter 104 of FIGURE 3 back one state.

I'nthe case: of thefadvancing of--the control counterld. ofFIGURE`-3,:asignal is applied .to the. AND circuit 138. from .the ORv circuitl.. This occurs whenthe :correctable errorcounter 122is in one of its higherstatesor-.when the Auncorrectableerrorcounter 124.,.is in one-.of apredetermined number of its higher states.. Thus, for-specie. example,with reference. to.- FIGURE 14, if the counter 122 Vis in state...5- or. arhigher.. state, `or if the. error counter- 124.is.in .state=3 .or any. higherstate, kupon the occurrence. of a sense. signalapplied on-lead152, an-advance pulse isapplied to.lead.106.=' This means thatifthe rate of occurrence of-correctableerrors,v orif the number-fof uncorrectable errors .exceeds a predetermined minimuml level in atime interval determinedlby the. rate of occurrencel of'sense and -reset pulses, thefsystemiwill bel stepped` to thenext more powerful :typeof error correcting scheme.

The lead154 tothefinhibiting linputterrninal of inhibit unit134 isconnected to receive-signalsfrom the switching. circuit v142.. associated with coun-ter122.- This arrangement is intended to. handlethe` situation whereoccasional infrequent .bursts of. noise. completely obliterate a portion of the. incoming` message. Under these circumstances', thecorrectable error-stepping counter willremain in` one of its ylowerrnost. states. However, .the uncorrectab'le er-` ror stepping` counter may reach state^3 or 4,1 for example. Under these conditions, it isnot worthwhile tosteplto the. next higher or morepowerful error correcting scheme. Accordingly, an inhibiting. signaljapplied on leadf154 prevents the applicationof anoutputpulse throughgthe AND circuit-135.58v to the-output lead 166,

Immediately. following.` the application vof sense signals to the leads. 15d` andJ1'52, resetsignalsare" applied to leads 153'andf16i). The. timeinterval'between successive sets of sense and reset pulsesis determined by the` master timing circuit 22..'l This. time.intervalcould, for example; be a matter offone or. more hundre'dsof' digit periods of the'messagetransmitted on'the data link. Suitable time intervalsmay readily'jbeAdetermined'by one' skilledin the artby the lerror 'characteristics ofthefdata link. Thus, for example, in cases'wherethe'datalink is subject'to rapid fluctuations inthe error rate, relatively `short time intervals between successive sets` of' sense andreset pulses would lb e required. On the other hand, wheretherate ofichange of'theerrorjrate is relatively'low, correspondin'glyflongertime intervals between the pairs ofsensc a'n`d reset pulsesare' permissable. In general, however, relatively short intervals' are" to jbe Vvpreferred in order to minimize thenecessary equipment in the required-control circuitsi The circuit OFFIGURESS asimple parity check-circuit which couldbe employed,l for example, as theencoder 31B 'shown in FIGUR'EI.y Thecircuit of FIGURE 5 is-an even parity check encoder circuit; that is, it provides la parity'checli, pulse if the number of information check pulsesis odd, Aand. thus' makes the' total numberf'ofA pulses in agiven word"or"code group'even. In a. circuit of FIGURES, lSinformation' bits orbinary digits are transmitte'd, a-ndthis'4 group of fifteen lbits is-follewed by a single paritycheck bit. `Sucha group ofl standa-rdlength code groups is known'asA a wordfin digital computer terminology.. The timing for the fy parity check encoder of FIGURE v5Y is` provided bythe ring counterv16t.k This ring counter 164 has' sixteen'states. The first-fteen states are'connected to the inputs ofthe OR circuit 166.Y Output signalsjfrom the- OR; circuit166 are applied-onleads 168 througlrthe switch 45" of FIGURE'l to thebuier storage circuitl The. determination ofthe odd-oreven character ofthe fifteen input' binary digits is made by the single stagecounter circuit'17t1; Input information digits are supplied to the circuit`170 on lead 172 from the buffer store. In additionto being applied to the counter circuit 170, theinformation digits are transmitted on lead 17.4 to the- OR circuit 176-. After passing through a suitable padding 'delay'circu'it 178, they' are transmitted to the data link on lead w01' envases The single stage counter circuit 17d includes the OR circuits 182 and 202, the AND circuit 184, the inhibit circuit 186, and the single digit period delay circuit 188. The designation 1D in the delay circuit les indicates that it includes one digit period of delay. The other circuit components are assumed to operate instantaneously. The counter circuit is of the dynamic type and includes a delay loop through which a pulse may circulate. The `state of the counter is determined by the presence or absence of a pulse in the loop including the ci-rcuit components 132, 186 and 188i. An initial pulse from lead 172 is inserted into the delay loop by 'the OR circuit 182. If there is a pulse circulating in the delay loop, the application of an additional pulse on lead 172 eliminates the pulse from the delay loop. Thus, for eX- ample, the pulse circulating through the delay loop will appear as one input to the AND circuit 164. The new pulse applied on lead 172 provides the other enabling input to the AND circuit 184. Under these circumstances, an inhibiting signal is applied on lead 190 to the inhibiting input terminal of the inhibit circuit 186. This has the effect of blocking the signal which would otherwise be transmitted from the OR circuit 182 through the inhibit unit 186. The next subsequent input pulse on lead 172 is, of course, transmitted through OR circuit 182 and starts circulating in the delay loop.

Upon the stepping of the counter 164 to its sixteenth state, a signal is applied on lead 192 to the enabling input to AND circuit 196. The pulse is designated W.P. No. 16, yas it is a word pulse which occurs in the sixteenth digit period of each word. This gates the pulse circulating in the memory loop of counter 1719 out to the OR circuit 176, if the counter is in the odd state. However, if the counter is in the even state, and no pulse is circulating in the delay loop, the output lead 193 is not energized in the fteenth digit period, and no signal is applied from the output of delay circuit 188 to an input of AND circuit 196 in the sixteenth digit period. Accordingly, no pulse is transmitted to the OR circuit 176 or to the output lead 180. This conrms the even nature of the parity check signals, as it has been shown that an additional pulse is added only when the counter is in the odd state.

The number 16 word pulse is also applied through the OR circuit 2&2 to the inhibiting input terminal of the inhibit unit 186. This serves to eliminate circulating pulses from the delay loop and reset the counter circuit to its initial state.

As mentioned above, the buffer storage timing circuit is not enabled during the sixteenth digit period of each Word. Accordingly, no input signal is recevied on lead 172 at this time, and the parity check bit is combined in OR circuit 176 with the first fifteen digits of the binary word to make a complete sixteen bit word which always includes an even number of digits. It may be noted that odd parity may readily be employed instead of even parity, and is often preferred so that every word includes at least one bi-t. The circuit of FIGURE 5 may readily be transformed into an odd parity check circuit by the addition of a negation circuit at the input to the AND circuit 196 from the delay circuit 188.

The circuit of FIGURE 6 is more fully disclosed in D. W. Hagelbarger application Serial No. 732,385, filed May l, 1958, and entitled Continuous Digital Error Correction System, now Patent No. 2,956,124, granted October 1l, 1960. The circuit of FIGURE 6 is that shown in Ithe Hagelbarger application modified to facilitate inclusion in the system of FIGURE 1 of the present application. In the circuit of FIGURE 6, the encoder, in the upper portion of the FIGURE, includes the encoding shift register 202, and its associated parity check encoding circuit 2114. Information digits are supplied from the buer storage circuit through the switch 41 to the shift register 2112. Timing signals are supplied from the timing circuit 265 through the switch 45 to the buer storage circuit. The encoding lcircuit of FIGURE 6 has a redundancy of fifty percent, that is one information bit is transmitted for each check bit. The interleaving of information bits from the shif-t register 202 with check bits from the parity check circuit 204 is accomplished by the switch 2196 which is operated under the control of the timing circuit 2%'. It may also be noted fthat the switch 207 which sorts out information and check bits at the decoder is operated in synchronism with the switch 206.

Correction of erroneous signals is possible at the delcoder ythrough the inclusion of each information digit into two check groups. Each of these check groups includes two information digits and one check digit. Thus, for example, the information digits in shift register positons 7 and 4 of shift register 292 are sampled on leads 2% and 21d, and an appropriate output parity bit from circuit 204 is supplied to the switch 2%. The value of the parity signal depends on the parity of the signals received on leads 2% and 210. Two parity check groups, each of which include a common information digit, are yshown at 212 and 211i in diagrammatic form and associated with the digital data link. The first check group, as represented by the line 212 and its depending arrows, includes the digits C1, D4, and D7. The second check group, as represented by the line 214 and its associated arrows, includes the check digit C4, and the information digits D7 and D10. In 'this regard, it may be noted that the information digit D, is common to these two check groups. Now, at the receiver, the simultaneous occurrence of failures in two parity check groups which are monitored in accordance with the arrows associated with lines 212 and 214i, would indicate that the informa- Ition digit D7 is in error. It would accordingly be reversed in the manner described below.

rIhe decoder circuit includes an information digit shift register having a first portion 216 and a second portion 21S, a check digit shift register 220, a first parity check circuit 222, and a second parity check circuit 224%. The check circuit 222 checks the validity of a check group coriresponding to that designated by line 212, while the second circuit 224 checks the parity of the group of digits corresponding to the line 21d. Failure indications from the parity check circuits 222 and 224 are indicated on leads 226 and 223, respectively. The AND circuit 230 is operative to reverse the digit stored in stage 7 of shift register 216 as it is transferred to shift register position 6, when both input leads from the two parity check circuits 222 and 224 are energized. In addition, a signal is applied to lead 232 to be transmitted to OR circuit 12S of FGURE 4 upon the occurrence of a correctable error.

Signals from the parity check circuits 222 and 224 are laiso applied to the uncorrectable error detection circuit 234. The uncorrectable error detection circuit 234 may take the form as shown in the application of D. W. Hagelbarger noted above. While the error detection 234 may be relatively complex, it may also be implemented by relatively simple counter circuits. Thus, for example, in the case of an error indication from parity check circuit 22d which is not foliowed by an error signal from parity check circuit 222 after exactly three digit periods, this is a prima facie indication that an error has occurred. In View of the fact that uncorrectable error indication from the circuit 234 normally indicates that at least two digits have been received erroneously, the pulse doubler 236 is provided. With this arrangement, advance signals to the stepping counter 124 of FIGURE 4 will represent to a closer approximation the actual number of erroneous digits which have been received and not properly correctcd by the decoder. it is again noted that further details of the circuit of FIGURE 6 and related scheme which may be used in the implementation of the present invention are set forth in the application of D. W. Hagelbarger cited above.

With reference to FIGURE l, it is noted that the com- .quantity having examples.

9. pound.y encoder ilis Imerely intended vto represent the presence of. anumber of different encoding-schemes .of various. error correcting capacities and/ or redundancies. Similarly, of course, the compounddecoder 2@ merely represents. tl1e..use of. various corresponding decoding schemes. The number. ofencoding and decodingschemes may vary'from two -to as large, a number as is 4desired-or required-by the-data link whichv isbeing employed; It mayalso be noted thatthe encoders.anddecodershave been shownasbeingrelatively independent; however, timing circuitsare shown used in common, and the error correcting and errory evaluationcircuits are. also shown as being employed jointly. It is also contemplated that .many ofthe components employed inthe encoders 30,132, and 3.4. and in the decoders, 38, andr 40'. may be used.in common, with switching circuits being provided to-switch the` needed component fromone error correctingscheme to the next.

The=timing circuit 22. of. FIGURE lmay include a master timingor clock source of pulses and circuitry for deriving desired control or program pulses at submultiples of the clock frequency. Techniques for obtaining program or-timing control pulses are now well known inthe. digital 'datahandling art. vThe timing circuit 22 may, for example, include afast ring counter of the type shown at 164 in FIGURE 5 of the drawings, anda slow ring counter whichwis advancedby one state each time the fast ringcounter completes a cycle of operation. By coupling an A-ND circuitto the outputs of` predeterminedstages oboth counters, a. digit pulse may hev obtained in any desired-digit periodiny theicomplete timing cycle-f of the timing circuit.

The error detectionschemesl described above generally involve the addition of checkdigits to `information digits. rlhe principles of thepresentinvention arealso applicable to coding schemes in which input digitalsignals are` translatedin a mannersuch thatthey donot appear directly in the redundant signalsappliedjto the data link. Onetechnique for implementing suchA a system could involve the inclusion of atranslation matrix in thebufier storageicircuit of 'FIGUREZ between the leads 71through 'iand the AND` gatesSij through.. 56; When employed in accordance with the present invention, individual translation. matrices. providing ditlerent redundancies would be switched into the buer storagel circuit, and no separate encoding circuit fwouldbe required. In each case, code groups sutlixedwith a marker. bit would be inserted inthe bu'er circuit shift register at its output end.

Inthe illustrative system shown in thev drawings, the error rate signalsaredetermined4 directly. Error rate signals could also be .derived from the measurement of. a a knownl relationship to the actual error rate.` Thu s,rfor example, in some systems sunspot activity bears a known relationship to the error rate. In other systems, electrical storms, the` distance betweenstations, and otherfactors havea close relationship to the error rate.

vThe term errorerate signals as employed in thepresent specifications and claims includes these variousparameters having-aknown relationship to the actual-error rate.

The datalink of FlGUREV l may be an extended transmission facility or a digital sorter or store, forA specic ln the case ofanextended transmission facility, duplicate.steppingcounters such as .that shown at 104 in FIGURE Bmaybe provided at the two terminals. DependingV onthe. type of error ratedetermination circuit which is employed, switching control signals mustbe sent from the decoding terminal to the encoding terminal or vice versa. In the casegof indirect parameters, such as those discussed inthe preceding-paragraph, the signals may be sent over the data link. When the error rate signals are detected directlyl as shown in FIGURE 4, however, signals for advancing the switching control counter or stepping it backmust be transmitted from the decoder to the encoder on a coded and time-shared basis, or otherwise, -depending on trac and other engineering factors.

l encoded by said encoding circuitry Whenthedata link isf-a digital sorter or store., however, the direct switching control connections showninthe presentdrawings are practical andv may be employed.-

Additional background material which may. well. be mentioned for the sake of completeness at this. point include. ar copending..application Serial No. 693,452 of W. D; Lewisandmyself entitled MultipleError Cor,- rection Circuitry, tiledwOctober 30, 1957 now Patent 2,954,433, granted September 27, 1960. Theerror cor.- rectiou scheme. disclosed in that-application is eminently suitable for inclusion in. the present. compound' error handling sys-tem. ln thisregard, it may betparticularly noted that both correctable and uncorrectable error-cir.- cuitsv are provided.. Concerning thelogic circuitv components, such as AND circuits, OR circuits, vand the like, reference is. made toanearly. article by J. H. Felker en titled.. Regenerative Amplifier for Digital Computer. Applications, which appearedat. pages 1584 through.l596 yof` the November v1952` issue -ofy the Proceedings. of the Institute Iof Radio Engin-eers, Volume 40, Number l1. Thecircuits of the present invention may be vimplemented iu-accordance with.thetechnologyv disclosed in the Eelker article, or in accordance with any. of the many other systems of logic' building blocks which have been disclosed. intexts and articles. on this subjectwhichappeared in the last ten years.

lt-is .to be understood that the .above-described arrangements-are illustrative of the application of-the principles of lthe invention. Numerous other arrangements.rnay be devised. by those skilledA in the art Without depart-ing from the4 spiritand scope of the invention.

What is claimed is:

l. A.digital data system comprising a.source. of. input digital-signals, compound .single passencoding circuitry including meansy for transmitting-signals in accordance With-different. digital coding schemes. of ditferentiredundancies, compound decoding circuitry including. means for decoding signals encoded by. said encoding. circuitry, a digital. data link.interconnecting\said-.encoding and saiddecodingcircuitry, meansfor generating signalsindicating-the rate of occurrence of4 errors on said data link-and means responsive to. saiderrorrate signals for automatically switching saidencodingand decodingcircuitry from one of'said different digitallcoding schemes toY another.

2: In4 a digital datal system, a source of input digital signals, a compound encoder for adding check digits to theI input'n digital signals, saidencoder'including'means lfor transmittingsignals inaccordance -with different digital `encoding schemes providing y different error correcting capacities and having diierent redundancies, aY corresponding compound decoder for correcting errors-.in the transmitted signals and' means for automatically switching from; one of .said-schemes -to another.l

3. In. a digital. data system, a source of input digital signals, a compound. encoder including meansiontransmitting, signals, in. accordance with. different digital; encodingschemesproviding different` error correcting capacities and different redundancies, meansfor generating signals indicating the rate of occurrence of correctable anduncorrectable errors for the one of `said schemes currently in use, 4and means for automatically switching 'from' one of said-schemes to another in responsel to said err-or rate sig-nals'.

4. AA digital data system comprising a'source-of input digital signals, 'compound encoding. circuitry including means'for transmitting signals in accordance with different digital coding schemesot different redundancies, buffer storage lcircuit means connected between said source and said. encoding circuitry for transmitting input signals to said encoding circuitry. in accordance with timing signals supplied by said encoding circuitry, compound decoding circuitry including means for decoding signals a digital Idata link interconnecting said encoding and said decoding circuitry,

adresse means for generating signals indicating the rate of occurrence of errors on said data linl; during the processing or' random input digital signals, and means responsive to said error rate signals for automatically switching said encoding and decoding7 circuitry from one coding scheme .to ano-ther.

5. In a digital data system, a source of input digital signals, a compound encoder for adding check digits to the input digital signals, said encoder including means for transmitting signals in accordance with different digital coding methods providing different error correcting capacities, and means for automatically switching from one of said digital coding methods to another of said digital coding methods.

6. ln a digital data system, a source of input digital signals, a compound encoder for adding check digits to the input digital signals, said encoder including means for transmitting signals in accordance with diiierent digital coding schemes providing different error correcting capacities and having diiierent redundancies, means for generating signals indicating the rate of occurrence of correctable errors for the scheme currently in use, means for generating signals representing the rate of occurrence of uncorrectable errors for the scheme currently in use, and means for switching from one of said schemes to another in response to both of said two types of error rate signals.

7. In a digital data system, a source of input digital signals, a butler storage circuit connected to receive signals from said source, a compound encoder connected to said buffer storage circuit for adding check digits to the input digital sivnals and for supplying timing control signals to said buffer storage circuit, said encoder including means for transmiting signals in accordance with different digital coding schemes providing diiierent error detecting capacities, and means for automatically switching from one of said schemes to another and concurrently changing the rate at which timing signals are applied to said butler storage circuit.

8. In a digital data system, a source of input digital signals, a compound encoder for increasing the redundancy of the input digital signals, said encoder including means for transmitting signals in accordance with different digital coding schemes providing dilerent error detecting capacities and different redundancies, means for counting errors for the scheme currently in use during the processing of random input digital signals, means for periodically sensing the output of said counting means and for resetting said counting means, and means for automatically switching from one of said schemes to another in response to the sensed output of said error counting means.

9. In combination, a source of digital input information, a buffer storage circuit coupled to said source, a digital data handling system, a compound encoding circuit including a simple parity checl: error detection encoder and a single pass parity check error correction encoder, and means for selectively and automatically switching either said simple parity check encoder or said error correction encoder into circuit between said buffer storage circuit and said `data handling System.

lO. In combination, a source of digital input information, a buffer storage circuit coupled to said source, a digital data link, a compound encoding circuit including a simple parity check error detection encoder and a single pass parity check error correction encoder, means for generating error rate signals, and means for selectively and automatically switching either said simple parity check encoder or said erre-r correction encoder into circuit between said butter storage circuit and said data link in accordance with said error rate signals.

1l. ln combination, a data system, means for providing said system with an error detection scheme, means for providing said system with a single pass parity check type error correction scheme of higher redundancy than said error detection scheme, means responsive to high error rate conditions for automatically switching fromI Said error detection scheme to said error correction scheme, and means responsive to low error rate conditions for switching from said error correction scheme to said error detection scheme.

l2. In combination, means for handling digital information in accordance with different digital encoding schemes having different error detection and correction capabilities, first and second error rate circuits, means for applying signals representing correctable errors for the scheme currently in use to said rst error rate circuit, means for applying signals representing uncorrectable errors to said second error rate circuit, and means for switching from one of said schemes to another when either of the error rates exceeds predetermined toleration limits.

13. ln combination, means for handling digital information in accordance with different digital coding schemes having different error detection and correction capabilities, first and second error rate circuits, means for applying signals representing correctable errors to said first error rate circuit, means for detecting uncorrectable errors for each scheme, and means for weighting the detected signals representing uncorrectable errors to provide signals approximating the number of uncorrectable received digits, means for applying the weighted signals to said second error rate circuit, and means for switching from one of said schemes to another in accordance with control signals developed from' said error rate circuits.

14. ln combination, a data processing system, means for providing said system with an error detection scheme, means for providing said system with at least one error correction scheme by which information is processed at higher redundancics and with a diierent digital code than with said error detection scheme, means for determining the rate of occurrence of uncorrectable errors with the scheme in use at any time, means for determining the rate of occurrence of correctable errors, if any, with the scheme in use at any time, and means for shifting from one of said schemes to another in response to the determined error rates. i

l5. ln combination, means for processing digital information in accordance with different digital coding schemes having different error detection and correction capabilities, first and second error rate circuits, means for applying signals representing correctable errors for the scheme currently in use to said iirst error rate circuit, means for applying signals representing uncorrectable errors to said second error rate circuit, means for switching from one of said schemes to another when either of the error rate exceeds predetermined toleration limits, and inhibiting means for preventing the operation of said switching means to a more powerful error correction scheme when the correctable error rate is below a predetermined level.

16. In combination, means for processing digital information in accordance with different digital coding schemes having ditterent error detection and correction capabilities, means for generating an error rate signal in accordance with correctable errors only, and means for switching from one of said schemes to another in accordance with the magnitude of said error rate signal.

17. In a digital data system:

a source of input digital signals;

a compound encoder, said encoder including iirst means for transmitting signals in accordance with a rst digital coding method providing one level of error correcting redundancy and also including additional means for transmitting signals in accordance with a second different digital coding method providing a diilerent level of error correcting redundancy;

a corresponding compound decoder including means for decoding signals coded in accordance with said first method and additional means for decoding signals coded in accordance With said second method;

a digital data link interconnecting said encoder and said decoder;

means for generating signals indicating uncorrectable errors for the one of said encoding methods in use; iand switching means responsive to said error indication means for concurrently switching said encoder and said decoder from one of said coding methods to another of said coding methods.

References Cited in the le of this patent UNITED STATES PATENTS Hamming et al Dec. 23, 1952 Hat-ton et ai Feb. 1, 1944 H-arris Nov. 22, 1955 Albrighton et al Aug. 6, 1957 Cory Nov. 12, 1957 Lukoff et al Feb. 14, 1961 Henning May 9, 1961 FOREIGN PATENTS Australia Oct. 24, 1957 

1. A DIGITAL DATA SYSTEM COMPRISING A SOURCE OF INPUT DIGITAL SIGNALS, COMPOUND SINGLE PASS ENCODING CIRCUITRY INCLUDING MEANS FOR TRANSMITTING SIGNALS IN ACCORDANCE WITH DIFFERENT DIGITAL CODING SCHEMES OF DIFFERENT REDUNDANCIES, COMPOUND DECODING CIRCUITRY INCLUDING MEANS FOR DECODING SIGNALS ENCODED BY SAID ENCODING CIRCUITRY, A DIGITAL DATA LINK INTERCONNECTING SAID ENCODING AND SAID DECODING CIRCUITRY, MEANS FOR GENERATING SIGNALS INDICATING THE RATE OF OCCURRENCE OF ERRORS ON SAID DATA LINK, AND MEANS RESPONSIVE TO SAID ERROR RATE SIGNALS FOR AUTOMATICALLY SWITCHING SAID ENCODING AND DECODING CIRCUITRY FROM ONE OF SAID DIFFERENT DIGITAL CODING SCHEMES TO ANOTHER. 